1. Field of the Invention
This invention relates to structures and methods of assembly of integrated circuit chips into interconnected multiple chip modules. More particularly, this invention relates to multiple chip structures connected physically and electrically.
2. Description of the Related Art
The manufacture of embedded Dynamic Random Access Memory (DRAM) requires that process parameters that enhance the performance of the logic or the DRAM, if separately formed on semiconductor chips, be compromised when DRAM is embedded into an array of logic gates on the same semiconductor chip. This compromise has limited the application of embedded DRAM. If there is no compromise in the process parameters to enhance the performance of logic or the embedded DRAM, the manufacturing process becomes very complicated and costly. Moreover, because of the structure of the embedded DRAM and the logic, burn-in of the embedded DRAM is not possible and embedding of DRAM with logic is not a reliable design solution.
A multiple chip module structure is a viable alternative to embedded DRAM. With multiple chips connected in intimate contact, the process parameters that maximize the performance of the DRAM chip and the logic gates can be applied during manufacture. Refer to FIG. 1 for a description of a xe2x80x9cchip-on-chipxe2x80x9d structure 100. Such a xe2x80x9cchip-on-chipxe2x80x9d structure is described in U.S. Pat. No. 5,534,465 (Frye et al.). A first integrated circuit chip 105 is attached physically and electrically to a second integrated circuit chip 110 by means of an area array of solder bumps 115. The process of forming an area array of solder bumps 115 is well known in the art and is discussed in Frye et al. 465. The second chip 110 is then secured physically to a substrate 120. Electrical connections 125 between the second integrated circuit chip 110 and external circuitry (not shown) are created as either wire bonds or tape automated bonds. The module further has a ball grid array 130 to secure the structure to a next level of packaging containing the external circuitry. Generally, an encasing material 135 is placed over the xe2x80x9cchip-on-chipxe2x80x9d structure 100 to provide environmental protection for the xe2x80x9cchip-on-chipxe2x80x9d 100.
U.S. Pat. No. 5,481,205 (Frye et al.) teaches a structure for making temporary connections to integrated circuit chips having xe2x80x9csolder bumpsxe2x80x9d or connection structures such as ball grid arrays. The temporary connections allow temporary contacting of the integrated circuit chip during testing of the integrated circuit chip.
The handling of wafers from which the integrated circuit chips are formed and the handling of the integrated circuit chips themselves causes the integrated circuit chips to be subjected to electrostatic discharge (ESD) voltages. Even though connections between the first integrated circuit chip 105 and the second integrated circuit chip 110 are relatively short and under normal operation would not be subjected to ESD voltages, ESD protection circuitry is required to be formed within the interchip interface circuit to provide protection or necessary driving capacity for the first integrated circuit chip 105 and the second integrated circuit chip 110 during burn-in and other manufacturing monitoring processes.
U.S. Pat. No. 5,731,945 and U.S. Pat. No. 5,807,791 (Bertin et al.) teach a method for fabricating programmable ESD protection circuits for multichip semiconductor structures. The interchip interface circuit on each integrated circuit chip is formed with an ESD protection circuit and a switch to selectively connect the ESD protection circuit to an input/output pad. This allows multiple identical chips to be interconnected and redundant ESD protection removed.
The circuits at the periphery of integrated circuit chip s generally are specialized to meet the requirements of standardized specifications. These include relatively high current and voltage drivers and receivers for communicating on relatively long transmission line media. Alternately, as shown in U.S. Pat. No. 5,461,333 (Condon et al.) the interface may be differential to allow lower voltages on the transmission line media. This requires two input/output pads for transfer of signals.
U.S. Pat. No. 5,818,748 (Bertin et al.) illustrates a separation of chip function onto separate integrated circuits chips. This allows the optimization of the circuits. In this case, EEPROM is on one integrated circuits chip and drivers and decoders are on another. The chips are placed face to face and secured with force responsive self-interlocking micro-connectors.
FIGS. 2a and 2b show multiple xe2x80x9cchip-on-chipxe2x80x9d structures 100 constructed on a wafer. Not shown is the forming of the first integrated circuit chip on a silicon wafer. The first integrated circuit chip is tested on the wafer and nonfunctioning chips are identified. The wafer is separated into the individual chips. The functioning first integrated circuit chips 105 then are xe2x80x9cflip-chipxe2x80x9d mounted on the second integrated circuit chip 110 on the wafer 200. The wafer 200 is then separated into the xe2x80x9cchip-on-chipxe2x80x9d structures 100. The xe2x80x9cchip-on-chipxe2x80x9d structures 100 are then mounted on the modules as above described.
An object of this invention is to provide a multiple integrated circuit chip structure where the interchip communication between integrated circuit chips of the structure have no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits with a minimal electrical load.
Another object of this invention is to provide a circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with test systems during assembly and test.
A further object of the invention is to provide a circuit to selectively connect internal circuits of the integrated circuits to one of two paths, either for single chip mode operation or for multi-chip mode operation.
To accomplish these and other objects, a multiple interconnected integrated circuit chip structure has a first integrated circuit chip physically and electrically connected to one or more second integrated circuit chips. The integrated circuit chips may be connected to one another by means of an area array of solder bumps. The first integrated circuit chip has interchip interface circuits connected to the one or more second integrated circuit chips to communicate between internal circuits of the first and second integrated circuit chips and test circuits. The test circuits are connected to the internal circuits of the first integrated circuit chip to provide stimulus and response to the internal circuits during testing procedures. Additionally, the first integrated circuit chip can be set to be operated in single chip mode, if desired.
The second integrated circuit chips have input/output interface circuitry to communicate with external circuitry connected to the second integrated circuit chips and to protect the second integrated circuit chips from electrostatic discharge voltages. Further, the second integrated circuit chips have interchip interface circuits connected to the first integrated circuit chip and to each other to communicate between the internal circuits of the chips and with test circuits. The test circuits are connected to the internal circuits of the second integrated circuit chips to provide stimulus to and response from the internal circuits during testing and burn-in procedures.
The interchip interface circuitry has an internal interface circuit for transferring electrical signals between the internal circuits of one integrated circuit chip to another integrated circuit chip. The interchip interface circuitry further has a mode select switch to selectively connect between the internal circuits of one integrated circuit chip and another integrated circuit chip or to operate in single chip mode, including stand-alone operation or connection to test interface circuits. The mode select signal to the mode switch is external to the chip. The signal may come from another of the integrated circuit chips, from the substrate, or from a test interface, or other external source. The mode switch has three terminals and a control terminal. The first terminal is connected to an output of the internal interface circuit, a second terminal connected to the internal circuitry, and the third terminal connected to an input/output interface. A mode selector is connected to the control terminal. The state of the mode selector determines the connection between the first terminal and thus the output of the internal interface circuit, the second terminal and thus the internal circuitry, and the third terminal and thus the test interface or other interface. During multi-chip mode operation, the first terminal is connected to the second terminal such that the internal circuits of two integrated circuits are connected through their respective internal interfaces. During single chip mode operations, the internal circuits are connected to an input/output interface. For example, during test and burn-in, the input/output interface may connect to external testing circuitry.
The first integrated circuit chip could be fabricated using a first type of semiconductor process and the second integrated circuit chip would be fabricated with a second type of semiconductor process that is not compatible with the first type of semiconductor process, and so on. As an example, the first integrated circuit chip could be an array of memory cells and the second integrated circuit chip would contain electronic circuitry formed with a process not compatible with a process of the array of memory cells. Alternatively, the second integrated circuit chip is an array of memory cells and the first integrated circuit chip contains electronic circuitry formed with a process not compatible with a process of the array of memory cells. Other integrated circuit chips could be fabricated in other ways. Fabricating the first integrated circuit chip using its optimum semiconductor process, fabricating the second integrated circuit chip using its optimum semiconductor process, and then joining the first and second integrated circuit chips by this invention creates a multiple chip integrated circuit structure having maximum performance with minimum cost.